ASIC/FPGA Design and Verification Engineer
Are you a design or verification engineer with ASIC/FPGA skills, and do you have a flair for client communication? If so, then SyoSil has a great career opportunity for you. We offer:
- A challenging role where you work closely with a highly skilled team as well as engineers in leading international companies
- Access to the latest technologies and ongoing professional development, including training with ASIC tools from top EDA vendors in the SyoSil partnership portfolio
- A competitive salary and a flexible working environment
SyoSil is a market leader in ASIC R&D space, including verification, design, device firmware and tool development. Our clients include top European and U.S. semiconductor companies working in specialised fields, such as the automotive, surveillance and telecommunication industries.
Join an international team of specialists
You will join a young and dynamic team of 16 engineers in a vibrant international environment close to central Copenhagen, Denmark. Contributing to large-scale project execution, you will collaborate closely with experienced and highly skilled colleagues who are all specialists within their field, giving you a unique opportunity to learn and grow.
Take part in large-scale project execution
As an ASIC/FPGA design and verification engineer, you will contribute to execution of projects on a large industrial scale, from concept and specification through RTL design to verification coverage closure. You will also deliver turn-key verification flows, verification IP and lead projects based on established and upcoming industry standards (SystemVerilog/UVM), helping clients improve their design and verification methodologies.
In relation to this, you can look forward to some international travel to liaise with clients and project execution.
The ideal candidate
While experience from the industry is a plus, it is not essential. What matters most is that you are highly skilled within ASIC/FPGA design, thoroughly systematic in your work and know how to manage parallel problems simultaneously. Furthermore, you need to have solid communication and presentation skills, enabling you to establish and develop strong client relations. In addition:
- You have a B.Sc. or an M.Sc. in electrical engineering or computer science, and you know how to debug complex systems in a traditional ASIC/FPGA design simulation environment.
- You have solid skills within RTL module design and/or verification, using Verilog/VHDL, and constrained random verification methodologies, such as SystemVerilog/UVM.
- It is a plus if you understand modeling environments such as SystemC.
- It is also an advantage if you are familiar with C++ or Python and able to debug complex software systems in a traditional Linux-based software environment.
- You speak and write English fluently, and preferably Danish too.
If you have any questions regarding the position, you are welcome to contact Kevin Steffensen at firstname.lastname@example.org.
Please apply for the position by sending your application to Peter Jensen at email@example.com no later than May 29th 2017.